RS595SXTSS16 8-Bit Shift Registers With 3-State Output

The RS595S series is an 8-bit serial-in/serial-out shift register with a storage register and three-state outputs. Independent clocks are provided for both the shift register and the storage register. The shift register has an asynchronous reset (MR) input, a serial (SER) input, and a serial output (Q7S) for cascading. A low level on MR clears the shift register. Data is shifted on a low-to-high transition of the SRCLK input. Data in the shift register is transferred to the storage register on a low-to-high transition of the RCLK input. If the two clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output as long as the output enable input (OE) is low. A high level on OE causes the output to assume a high-impedance off state. Operation of the OE input does not affect the state of the register.